The present invention relates to a nonvolatile semiconductor storage device and a method for operating the nonvolatile semiconductor storage device, and more particularly to a nonvolatile semiconductor memory device enhanced for data retention characteristics, accuracy of program and erase operations.
For a nonvolatile semiconductor storage device in which each memory cell is composed of an FET transistor provided with a floating gate covered by an insulating film therearound and used as a charge storing layer, data is stored by controlling the amount of electrons stored in the floating gate thereby changing the threshold voltage of the transistor. When programming or erasing data into or from the memory cell, electrons are either injected or ejected from the floating gate via the insulating film.
Electron injection/ejection is possible by using the (Fowler-Nordheim (F-N)) tunnel phenomenon and the hot electron phenomenon. At this time, electrons are injected in the insulating film around the floating gate with the application of a high electrical field. Consequently, when the number of program/erase cycles is increased, the insulating film receives an electron injection stress repetitively, thereby degrading the insulating film. This results in the degradation of the various properties of the memory cell. Especially, when a low electrical field is applied to the insulating film that has been degraded due to such repetitive program/erase operations, the leakage current (low electric field leakage current or stress-induced leakage current) is increased. Consequently, the electron retention characteristics or the disturb characteristics of the memory cell are degraded. This degradation has now been questioned as a factor to limit the program/erase cycles for such a nonvolatile semiconductor memory device.
For example, Mr. Endoh and others disclosed a method, as described in the first related art example, for improving the read disturb characteristics of memory cells by suppressing the above mentioned stress-induced leakage current in the 1994 International Electron Devices Meeting 3.3, and in the 1995 Springtime Applied Physics Academy Scientific Lecture Meeting (30p-R-6). Hereunder, the outline of this method will be described with reference to FIG. 4.
FIG. 4(a) is a timing flow of voltages applied to a memory cell in an erase operation. FIG. 4(b) is a cross sectional view of a memory cell. In the first related art example, data is programmed/erased in a memory cell by injecting/ejecting electrons in/from the floating gate 42 via the gate insulating film 46 rising the F-N tunnel phenomenon. In this example, ejection of electrons from the floating gate 42 is defined as an erase operation. If this erase operation is repeated many times using the F-N tunnel phenomenon, the gate insulating film 46 of each memory cell is degraded as described above, and as a result, the stress-induced leakage current is increased. In this first related art example, it is considered that an increase of the stress-induced leakage current occurs via many trap sites formed in the insulating film along with the progress of the degradation of the gate insulating film.
Therefore, in order to prevent this stress-induced leakage current in the first related art example, an erase operation is performed as to be described later, in order to deactivate trap sites as follows.
At first, the control gate is set to the ground potential and a predetermined positive erase voltage Vee is applied to the substrate 45, the source 43, and the drain 44 of an object memory cell. Then, electrons are ejected from the floating gate toward the substrate 45 via the gate insulating film 46 using the F-N tunnel phenomenon, thereby setting the threshold voltage of the memory cell to a predetermined erase level. At this time, trap sites in the gate insulating film 46 are activated by the applied high voltage Vee.
Immediately following this erase operation, a positive voltage Vgg is applied to the control gate 41 for a sufficient amount of time to deactivate the trap sites. The voltage Vgg must be a voltage that can suppress a program operation, that is, a low voltage that can suppress the variation of the threshold voltage from a predetermined erase level. The voltage Vgg must also have the same polarity as that of the read operation, and have a larger voltage than the voltage in the read operation.
With this application of the positive low voltage Vgg, the number of trap sites active in the read operation is reduced at the phase boundary between the gate insulating film 46 and the substrate 45, as well as near the phase boundary. And accordingly, the stress-induced leakage current is reduced, thereby making it possible to suppress the variation of the threshold voltage caused by a read operation and improve the read retention characteristics after that.
In a memory cell whose gate insulating film is degraded due to repetitive program/erase operations, however, a variation of the threshold voltage also occurs due to a leakage of many electrons trapped in the gate insulating film in addition to an increase of the stress-induced leakage current. Mr. Kato and others made this clear (referred to in the 1994 International Electron Devices Meeting 3.2).
It is well known that many charged trapping centers are formed in the gate insulating film depending on the program/erase operation method if the program/erase operation is repeated. When electrons pass through the insulating film during program/erase operation, some of the electrons are trapped by those charged trapping centers. Those trapped electrons leak more easily out of the insulating film than the electrons stored in the floating gate. The threshold voltage of the memory cell is thus varied sharply and quickly after a program/erase operation, thereby affecting the data retention characteristics significantly. Therefore, in order to improve the data retention characteristics of the memory cell, it is very important to reduce both the trapped electrons in the insulating film 46 and the stress-induced leakage current.
FIG. 13 shows the distribution of electrons trapped in the gate insulating film 46 during an erase operation of the first conventional technology. FIG. 13(a) is an explanatory view of the electron distribution when an erase voltage Vee is applied toward the substrate 45, and FIG. 13(b) shows an explanatory view of the electron distribution when a positive-low voltage Vgg is applied toward the control gate 41 after the application of the erase voltage. As shown in FIG. 13(a), when the erase voltage Vee is applied, some of the electrons ejected from the floating gate 42 to the gate insulating film 46 are trapped by the charged trapping centers existing near the floating gate 42 in the gate insulating film 46. In addition, electron ejection occurs near the phase boundary of the substrate in the gate insulating film 46 occurs electron ejection.
Consequently, the distribution of trapped electrons becomes as follows; too many electrons gather at the floating gate 46 side and fewer electrons gather at the substrate 45 side (or holes are excessive). If the application of the erase voltage Vee is finished in such a distribution state, too many electrons or holes are distributed in the gate insulating film 46, and as a result the inner electric field becomes a dominant force. Electrons or holes are then ejected from the gate insulating film 46 to ease this dominant force. This phenomenon, however, invites a variation of the threshold voltage, which will reduce the margin between the threshold voltage and the program level of a memory cell from which data is erased. As a result, the data retention characteristics of the memory cell is degraded.
In the first related art example, trap sites are deactivated with a positive low voltage Vgg, which is applied after the application of an erase voltage Vee to suppress the stress-induced leakage current. The voltage Vgg is a little higher than that in the read operation. In this case, trapped electrons in the gate insulating film are also ejected in small amounts. However, since the electric field applied to the gate insulating film with the low voltage Vgg is as low as about 3 to 5 MV/cm, it is impossible to eject the electrons trapped in the insulating film satisfactorily with a high electric field applied in program and erase operations.
Furthermore, each of general nonvolatile semiconductor memory devices includes a memory cell array composed by integrating many memory cells. In this case, generally, the erase characteristics of each memory cell are varied due to a process variation, and also due to a degradation tendency variation with respect to repetitive program/erase operations. In other words, the amount of electrons that will be trapped in an insulating film during an erase operation, as well as the threshold voltage variation characteristics after an erase operation may be varied among memory cells. If a voltage Vgg is applied again to memory cells from which data has already been previously erased, just like in the first related art example, some of those memory cells will not be able to secure a predetermined level threshold voltage, since a program operation is executed in them and trapped electrons are ejected from them as described above. Therefore, in order to prevent such problems, an operation is needed to verify the threshold voltage after the low voltage Vgg is applied. If there are any memory cells in which the threshold voltage does not satisfy a predetermined erase level after the low voltage Vgg is applied, another erase operation must be executed. In the case of the first conventional technology, in which the low voltage Vgg is applied only once after an erase operation is finished, however, it is impossible to prevent such a variability.
Next, the nonvolatile semiconductor memory device in the second related art example will be described. This device is disclosed in the official gazette of Japanese Unexamined Patent Publication No. 7-122091. In the second related art example, the program characteristics are recovered by suppressing the trapping of electrons in the insulating film, which is caused by repetitive program/erase operations. Hereunder, the outline of this operation method will be described with reference to FIG. 5.
FIG. 5(a) is a flow chart indicating an erase operation in the second related art example. FIG. 5(b) is a cross sectional view of a memory cell with respect to the voltages applied for programming. The nonvolatile semiconductor memory device in this second related art example has program, read, erase, and stress apply modes. For a program operation for such a memory device, the substrate 45 and the source 43 are set to the ground potential, a predetermined positive voltage Vd is applied to the drain 44 and a high voltage VPP is a applied to the control gate 41. The, hot electrons generated with a high electric field applied between the source 43 and the drain 44 are injected in the floating gate via an area near the drain 44 of the gate insulating film 46 using a high voltage Vpp applied to the control gate 41, as shown in FIG. 5(b). At this time, some of the injected electrons are trapped in the gate insulating film 46. Therefore, as program/erase cycles are repeated, the electrons trapped in an area around the drain 44 of the gate insulating film 46 are increased, and, as a result, those trapped electrons ease the electric field of the gate insulating film 46 in the vertical direction during a program operation and slow down the program operation.
Therefore, in order to avoid such a problem, in the case of an erase operation in the second related art example, the stress apply mode is set after a program operation is performed first, in order to eject electrons trapped in the gate floating film 46 to the floating gate 42 as shown in FIG. 5(a). The object erase operation is executed after this. The stress apply mode mentioned here refers to a mode in which, for example, the substrate 45 and the source 43 are opened. The supply voltage Vcc is applied to the drain 44 and a high voltage Vpp is applied to the control gate 41. By ejecting trapped electrons beforehand in such a way, it is possible to keep the original program operation speed in the subsequent program operations.
However, in the case of the second related art example, shown in FIG. 5(a) , a program operation is executed, and the stress apply mode is set to eject the electrons trapped in the gate insulating film 46 to the floating gate 42. An object erase operation is executed after this. The erase operation is then verified. In such an operation method, when an erase operation is executed, electrons are trapped again in the gate insulating film 46.
Those trapped electrons come to affect the threshold voltage read in such a verify operation. This makes it impossible to suppress the variation of the threshold voltage caused by the leakage of those trapped electrons. In addition, in the case of the second related art operation method, an operation for applying a stress of 1 to 20 ms is added in addition to a program operation, an object erase operation, and a verify operation for the erase operation. However, this causes another problem of increasing the erasing time.
As described above, the first related art technology deactivates trap sites by applying a positive low voltage Vgg in order to suppress the stress-induced leakage current after an erase voltage Vee is applied. The voltage Vgg is set a little higher than that applied in read operations. At this time, some of the trapped electrons are also ejected from the gate insulating film 46. However, since the electric field applied to the gate insulating film 46 with the voltage Vgg is as low as about 3 to 5 MV/cm, it is impossible to eject the trapped electrons from the gate insulating film 46 satisfactorily within a short time with the high electric field that is applied during program and erase operations.
If a low voltage Vgg is applied again to memory cells for which an erase operation has already been performed once, just like in the first related art example, some memories cannot secure a predetermined erase level threshold voltage. This is because a program operation is performed or trapped electrons are ejected as described above. Therefore, in order to avoid such a problem, the threshold voltage must be verified after the low voltage Vgg is applied. If there are any memory cells in which the threshold voltage does not satisfy the predetermined erase level after the voltage Vgg is applied, an erase voltage Vee must further be applied. The first related art operation method, in which the low voltage Vgg is applied only once after an erase operation is finished cannot prevent this variation of the threshold.
In the case of the second related art operation method, an erase operation performed in the stress apply mode as described above, allows electrons to be trapped again in the gate insulating film 46. Consequently, the threshold voltage read in the verify operation performed after the erase operation is affected by those trapped electrons. It is thus impossible for the related art operation method to suppress the variation of the threshold voltage caused by the leakage of the trapped electrons.
In the second related art operation method, another problem also arises of increasing the erasing time, since an erase operation in this method requires an additional operation for applying a stress of 1 to 20 ms in addition to a program operation, an object erase operation, and a verify operation.
Under such circumstances, it is an object of the present invention to provide, a nonvolatile semiconductor memory device that can eject electrons trapped in the gate insulating film within a shorter time than the related art method and suppress the variation of the threshold voltage even when characteristics are varied among memory cells, as well as provide a method for operating such a nonvolatile semiconductor memory device.
The nonvolatile semiconductor memory device of the present invention has a memory array consisting of a plurality of memory cells, each being formed with a gate insulating film, a floating gate electrode, an insulating film between electrodes, and a control gate electrode formed respectively in a first conductor type semiconductor area, as well as a second conductor type source area, and a second conductor type drain area formed, respectively, in the first conductor type semiconductor area, wherein program and erase operations are performed by controlling the amount of electrons in the floating gate electrode.
The nonvolatile semiconductor memory device of the present invention further includes at least means for applying the predetermined first operation voltage to each of the memory cells in order to inject or eject electrons in or from the floating gate electrode; means for applying the second operation voltage to the memory cell after the application of the first operation voltage to give an electric field with a polarity opposite to that of the electric field, given with the application of the first operation voltage to the insulating film area around the floating gate through which electrons pass when the first operation voltage is applied; means for verifying the threshold voltage of the memory cell after the second operation voltage is applied; and means for deciding whether to repeat the above operations following the application of the first operation voltage after the verify operation.
The method for operating the nonvolatile semiconductor memory device of the present invention, which has a memory cell array consisting of a plurality of memory cells, each of which is formed with a gate insulating film, a floating gate electrode, an insulating film between electrodes, and a control gate electrode formed respectively in a first conductor type semiconductor area. A second conductor type source area and a second conductor type drain area are also formed respectively in the first conductor type semiconductor area, wherein program and erase operations are performed by controlling the amount of electrons in the floating gate electrode. This comprises a process for applying the predetermined first operation voltage to the memory cell in order to inject or eject electrons in or from the floating gate electrode; a process for applying the second voltage to the memory cell after the application of the first operation voltage to give an electric field of a polarity opposite to that of the electric field given with the application of the first operation voltage to the insulating film area around the floating gate through which electrons pass when the first operation voltage is applied; a process for verifying the threshold voltage of the memory cell after the second operation voltage is applied; and a process for deciding whether to repeat the above operations following the application of the first operation voltage after the verify operation, in order to execute program and erase operations.
In this case, the second operation voltage should give an electric field of at least 7 MV/cm in absolute value to the insulating film area around the floating gate, and the pulse width of the second voltage should preferably be shorter than that of the first operation voltage.
The process for applying the second operation voltage to the memory cell should be executed when the number of program/erase cycles exceeds a predetermined amount.
In addition, each time the process for applying the first operation voltage to the memory cell is repeated by a predetermined amount, the pulse width of both the first and second operation voltages may be increased.
In this case, the process for increasing the pulse width of the second operation voltage may be executed until the pulse width of the second operation voltage reaches a predetermined value.
It is also possible that each time the process for applying the first operation voltage to the memory cell is repeated by a predetermined amount, a process for increasing the peak value of both the first and second operation voltages may be added.
In this case, the process for increasing the peak value of the second operation voltage may be executed until the peak value of the second operation voltage reaches a predetermined value.
In addition, the first operation voltage should preferably be applied to a predetermined word line, that is, a selected word line has a positive polarity voltage with respect to the ground potential, and the ground potential or a negative potential with respect to the substrate should be applied the ground potential, and the second operation voltage should be applied to the word line as a negative polarity voltage with respect to the ground potential.
It is also possible to apply the first operation voltage to a predetermined word line, that is, a selected word line, as a positive polarity voltage with respect to the ground potential, and the substrate should be applied the ground potential or a negative potential with respect to the ground potential, and the second operation voltage should be applied to the substrate as a positive polarity voltage with respect to the ground potential.
It is also possible to apply that the first operation voltage to the substrate as a positive polarity voltage with respect to the ground potential, and the second operation voltage is applied to one word line or to a plurality of word lines as a positive polarity voltage with respect to the ground potential.
It is also possible to apply the first operation voltage to a predetermined word line, that is, a selected word line, as a negative polarity voltage with respect to the ground potential, and the substrate is applied the ground potential or a negative potential with respect to the ground potential, and the second operation voltage is applied to the word line as a positive polarity voltage with respect to the ground potential.
It is possible that in each memory cell, the peak value or the pulse width of the second operation voltage is varied according to the program level that is set so as to allow information of a plurality of bits to be stored in the memory cell by setting the threshold voltage to any of a plurality of predetermined program or erase levels.
Hereunder, the preferred embodiments of the nonvolatile semiconductor memory device of the present invention, as well as its operation method will be described.
The nonvolatile semiconductor memory device of the present invention has a memory array consisting of a plurality of memory cells disposed in a matrix. Each of those memory cells is provided with a floating gate electrode formed in a first conductor type semiconductor area via a gate insulating film, and with a second conductor type source area and a second conductor type drain area formed respectively in the first conductor type semiconductor area. Data is programmed and erased in each memory cell of the nonvolatile semiconductor memory device by controlling the amount of electrons in this floating gate electrode. The nonvolatile semiconductor memory device of the present invention also includes at least: a circuit for generating a predetermined first operation voltage for injecting or ejecting electrons in or from the floating gate electrode, that is, a predetermined program/erase voltage to be applied to a selected memory cell; a circuit for generating a second operation voltage for giving an electric field to the selected memory cell with a polarity opposite to that of the electric field, given with the application of the first operation voltage to the insulating film area around the floating gate electrode through which electrons pass when the first operation voltage is applied; a circuit for generating a voltage to verify the threshold voltage of the memory cell after the second operation voltage is applied, that is, a circuit for generating a verification; and a circuit for deciding whether to repeat the above operations following the application of the first operation voltage after the verify operation by checking to see if the program/erase level for the memory cell is within a predetermined threshold voltage, that is, a circuit for deciding a program/erase level.
The method for operating the nonvolatile semiconductor memory device of the present invention applies a predetermined first voltage generated in the first operation voltage generating circuit to a selected memory cell, and then applies a predetermined second voltage generated in the second operation voltage generating circuit to the selected memory cell, then applies a verify voltage generated by the verify voltage generating circuit to the selected memory cell in order to make a verify operation. In addition, if the threshold voltage of the memory cell is not within a predetermined value after the verification, the operations following the application of the first operation voltage are repeated.
With an execution of this operation method of the present invention, electrons trapped in the insulating film during the application of the first operation voltage are ejected with the application of the second operation voltage before the verification. The nonvolatile semiconductor memory device of the present invention can thus suppress the variation of the threshold voltage of each memory cell, which is caused by a leakage of the trapped electrons, as well as improve the data retention characteristics.